Greg
I have requested the EMIFA experts on the team to look at this thread.
Minor follow up queries
1) I assume the EMA_WAIT signal is connected to NAND busy pin?
2) Clarify why is the clock limited to 92/100MHz. As per the OMAPL138 datasheet, pg 94, table 5-5 ASYNC1 domain that is source for EMIFA clock can allow 148 MHz for ASYNC mode and 100 MHz for SDRAM mode. I assume both the FPGA and NAND are async , is there something else driving the 100 MHz max limit?
3) I assume it is not acceptable to have NAND and FPGA traffic be atomic?
4) Is the EDMA-Q-TC dedicated for FPGA transfers , solely used for FPGA transfers? Is throttling the bandwidth on FPGA traffice acceptable? If so and this Q-TC is exclusively servicing just FPGA traffic, perhaps you can set the TC RDRATE register to higher than default, to allow throttling the FPGA data (will degrade throughput but perhaps provide better interleaving of traffic).
Regards
Mukul