HR:
Sorry,I cannot tell that clearly .
But,if it is in L2,I am sure that there is nothing because every core can occupy L2 memory space
separately Then I am not sure if the variable is located in the MSMC shared memroy or DDR.
Because with regarding to MSMC or DDR,they are shared together by all 8 cores.
Ok ,Let's back to the initial problem.This time in order to more clearly I take an array
for example below.
----------------------------------------
//core0 side
CMD file:
DDR3 : org = 0x8000 0000 len = 0x1000 0000
TEST_DATA > DDR3
#pragma DATA_SECTION(value_for_test,"TEST_DATA")
int value_for_test[100];
//core1 side
CMD file
DDR3 : org = 0x8000 00000 len = 0x1000 0000
TEST_DATA > DDR3
#pragma DATA_SECTION(value_for_test,"TEST_DATA")
int value_for_test[100];
-----------------------------------------------------
Like above situation ,Array value_for_test in core0 is located in the location address start from
0x8000 0000 and the same is for core1.What will happen ? Do the two value_for_test conflict ?
I am not sure.
For more,take a example, If at some situation,I memset value_for_test simultaneously from core0 side
and core1 side.For example: core0 memset 0xff, core1 memset 0xee
//core0
memset(value_for_test,0xff,sizeof(value_for_test));
//core1
memset(value_for_test,0xee,sizeof(value_for_test));
Then,what will happen? Should we avoid that situation ? Because it is unpredictably either for core0
or for core1.Do you agree me?