Hi,all :
I think more and more people block on the problem about how to use DDR3A and DDR3B on XTCIEVMK2X REV1.1.
I have blocked on this issue for several days,I have ask for help on the below post:
http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/300548/1057887.aspx#1057887
The above post have answered some part of my problem.But I have find a counter-example about that Rex said that Rev1.1 XTCIEVMK2X board just could access 1GB (only half of the DDR3A 2GB DIMM on board) because of
the bus width issue.So I asked on the below post again.
http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/306148.aspx
So,Those above posts are just what I have proposaled.Today I have seen Ram who also have posted the similar problem about DDR3A and DDR3B on this Keystone fourm on below post.
http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/306482.aspx
So I think that problem have been a popular one that more and more people have met when they went on.
Hi, TI keystone experts ,Would you response to those questions respectively listed in those above posts including mine and Ram's.such as:
According to DDR3A 2GB DIMM and DDR3B 1GB on board.
1.
which one (DDR3A or DDR3B) used by ARM?
which one used by DSP?
Or maybe, which one is also used by DSP and used by ARM too?
All up,How to allocate DDR3A and DDR3B by ARM and DSP?
2.
Is the bus width issue true or not true?
If true ,how to explain the counter-example that I find on the above post.
All in all,There are many questions twisted me with regarding to DDR3A and DDR3B.It's time to response to
these questions respectively .