It seems that on RC side you are running a Linux program and EP side is the PCIE ROM bootloader. Since the EP side BAR0 size is hard coded, and after PCIE handshaking, the granted BAR0 lenght is 0x1000 bytes from RC side by checking with pci_resource_start(). Then from RC side with BAR0 you can only access the PCIE application register of EP.
With RBL, there are also BAR1/2/3/4 configured depending the switch pin setting, there BAR length are pretty big. Can you use BAR0 to change the IB translation register of EP side for one of the LL2/MSMC/DDR or the unused BAR4 to point to 0x2180_1000 for configuration registers? Will this work?
We have some example in C:\ti\mcsdk_2_01_02_06\tools\boot_loader\examples\pcie\linux_host_loader\pciedemo.c, e.g.void HAL_readDMA(uint32_t srcAddr, uint32_t dstAddr, uint32_t size, uint32_t flag),
iowrite32(EDMA_TPCC0_BASE_ADDRESS, pReg + IB_OFFSET(3)/4);
pReg = (uint32_t*)ddrVirt; /* Now it points to the start of EDMA_TPCC0_BASE_ADDRESS */
Where IB_OFFSET(3) was used for DDR originally, we temporarily changed it to point to EDMA_TPCC0. In your case, can you change this to 0x2180_1000?
I am not familiar with DM8148 PCIE memory space, if EP's configuration register is memory mapped into RC's (FOR 6657, it is 0x2180_2000 region), you write to this mapped region of RC side is equal to writing to the configuration register of the remote EP.
Regards, Eric