Be glad to see your reply.
My configuration is to set the register of McBSP3 as below:
struct omap_mcbsp_reg_cfg mcbsp_cfg = {
.spcr1 = RJUST(0) | DXENA | RINTM(2),
.spcr2 = FREE | SOFT | XINTM(2) | XSYNC_ERR,
.pcr0 = FSXM | FSRM | CLKXM | CLKRM | CLKRP,
.rcr1 = RFRLEN1(0) | RWDLEN1(0),
.rcr2 = RPHASE | RFRLEN2(0) | RWDLEN2(0) | RCOMPAND(0) | RDATDLY(0),
.xcr1 = XFRLEN1(0) | XWDLEN1(0),
.xcr2 = XPHASE | XFRLEN2(0) | XWDLEN2(0) | XCOMPAND(0) | XDATDLY(0),
.srgr1 = FWID(7) | CLKGDV(186),
.srgr2 = FSGM | FPER(7),
};
Then I use the following code to initialize McBSP3:
mcbsp_id = OMAP_MCBSP3;
status = omap_mcbsp_request(mcbsp_id);
printk(KERN_ALERT "First cfg:\n");
DumpMcBSP_cfg(); //Dump all register value
omap_mcbsp_config(mcbsp_id, &mcbsp_cfg);
mdelay(1); //Wait for more than 2 clocks
mcbsp_cfg.srgr2 |= GSYNC;
printk(KERN_ALERT "Second cfg:\n");
DumpMcBSP_cfg();
omap_mcbsp_config(mcbsp_id, &mcbsp_cfg);
mdelay(1);
mcbsp_cfg.spcr1 |= RRST;
mcbsp_cfg.spcr2 |= XRST;
printk(KERN_ALERT "Third cfg:\n");
DumpMcBSP_cfg();
omap_mcbsp_config(mcbsp_id, &mcbsp_cfg);
mcbsp_cfg.spcr2 |= FRST;
mcbsp_cfg.spcr2 |= GRST;
printk(KERN_ALERT "Fourth cfg:\n");
DumpMcBSP_cfg();
omap_mcbsp_config(mcbsp_id, &mcbsp_cfg);
mdelay(1);
omap_mcbsp_set_io_type(mcbsp_id, OMAP_MCBSP_POLL_IO);
The output of the code above are:
First cfg:
spcr1=a0
spcr2=328
pcr0=f01
rcr1=0
rcr2=8000
xcr1=0
xcr2=8000
srgr1=7ba
srgr2=1007
Second cfg:
spcr1=a0
spcr2=328
pcr0=f01
rcr1=0
rcr2=8000
xcr1=0
xcr2=8000
srgr1=7ba
srgr2=9007
Third cfg:
spcr1=a1
spcr2=329
pcr0=f01
rcr1=0
rcr2=8000
xcr1=0
xcr2=8000
srgr1=7ba
srgr2=9007
Fourth cfg:
spcr1=a1
spcr2=3e9
pcr0=f01
rcr1=0
rcr2=8000
xcr1=0
xcr2=8000
srgr1=7ba
srgr2=9007
You can see no value same as you provided. I try to set the register as the value in your last reply. Then the system halt when execute the first omap_mcbsp_config(). Why?
I hope I can see your reply as soon. Thank you!
BR!
John