Part Number: TDA4VL-Q1 Tool/software: Hello TI exprits, In the BYD SA5 we meet a very strange issue,we configurated the main domain MSRam, https://e2e.ti.com/e2eprivate/valeo/valeo-ep-automotive/f/valeo-jacinto-forum/1373333/tda4vl-q1-can-mcu-domain-use-the-msram_512k0_ram-as-rw-data-region/5252249 in the previous tikets we have mentioned that. and we put some text section in the 0x80000 which we congfigured in the RAT function #define CSL_MCU_ARMSS_RAT_CFG_BASE (0x40f90000UL) #define MSRAM_RAT_REGION_INDEX 10U #define MSRAM_RAT_REGION_BASE (0x4F02000000UL) #define MSRAM_RAT_REGION_SIZE (0x80000UL) #define MSRAM_RAT_REGION_LOCAL_BASE (0x80000UL) void Rat_Msram512KBInit(void) { bool ratRetVal; CSL_RatTranslationCfgInfo translationCfg; uint32_t index = MSRAM_RAT_REGION_INDEX; /* Add RAT configuration to access address > 32bit address range */ translationCfg.translatedAddress = MSRAM_RAT_REGION_BASE; translationCfg.sizeInBytes = MSRAM_RAT_REGION_SIZE; translationCfg.baseAddress = (uint32_t)MSRAM_RAT_REGION_LOCAL_BASE; ratRetVal = CSL_ratConfigRegionTranslation((CSL_ratRegs *)CSL_MCU_ARMSS_RAT_CFG_BASE, index, &translationCfg); if (ratRetVal == false) { UART_printf("\nFailed to configure the RAT index %d address 0x%lx\n", index, translationCfg.translatedAddress); } } 00080000 00080000 00033020 00033020 rwx 00080000 00080000 00033020 00033020 rwx .main_Msram but currently we do some stress test and found that,some times when the sbl to copy the data from scratch memory to the main domain msram some of the text is not correct which load in the main domain MSARAM,but the text in the DDR and mcu msam is all correct. such as the text in the 0x81fb4 should be which the correct data is like bellows 81f9c: 03 10 a0 e3 mov r1, #3 ; ACTL_Parking_DW.is_P4U_OUT_SC = ACTL_Parking_IN_P4U_OUT_PSM_SC; 81fa0: c1 01 c4 e5 strb r0, [r4, #449] ; ACTL_Parking_DW.A_SIG_APA_PARKING_TYPE_SELD = ACTL_Parking_ACTL_PARKINGOUT; 81fa4: a5 01 c4 e5 strb r0, [r4, #421] 81fa8: 01 00 a0 e3 mov r0, #1 ; ACTL_Parking_DW.is_P4U_CTRL_ON_SC = ACTL_Parking_IN_P4U_OUT_SC; 81fac: b1 11 c4 e5 strb r1, [r4, #433] ; ACTL_Parking_DW.A_SIG_SET_DASW_MANEUVER_MODE = ACTL_Parking_ACTL_DASW_MM_PO; 81fb0: 9c 01 c4 e5 strb r0, [r4, #412] ; } 81fb4: 34 d0 8d e2 add sp, sp, #52 81fb8: f0 8f bd e8 pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} 81fbc: 00 f0 20 e3 nop ; if (((uint32_T)ACTL_Parking_DW.is_P4U_FAILURE_SC != 81fc0: b5 01 d4 e5 ldrb r0, [r4, #437] ; IN_P4U_5FAILURE_ST_FAILURETO_OF) && ((((uint32_T) 81fc4: 01 00 50 e3 cmp r0, #1 and I read the memory directly and found that there are 32bytes from 0x81fa0 to 0x81fbc which have been change to 0, and we also check the text in the main domain MSRAM, there are many place which have been changed such as here such as here such as here and all changed is 32 bytes which should be text code but was change to 0,is there any cache issue or dma issue? can we use the main domain SRAM for the mcu text code.Could you pls check is this methods which use main domain MSRAM in mcu domain is fine,can you check this with your IP design TEAM for this.
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