Dear Daolin, [quote userid="576780" url="~/support/processors-group/processors/f/processors-forum/1343344/am6422-icssg_prueth-port-initializing-but-not-able-to-connect/5185260#5185260"]the time offset is <2nS[/quote] 2nS is ideal delay for batter setup & hold time of RGMII signal. However, minimum 1nS setup & hold time of RGMII signal is acceptable by AM64xx & PHY. [quote userid="576780" url="~/support/processors-group/processors/f/processors-forum/1343344/am6422-icssg_prueth-port-initializing-but-not-able-to-connect/5185260#5185260"]Can the layout files be provided for our hardware team to review?[/quote] I have attached e2e.ti.com/.../PRU_5F00_ICSSG_5F00_Ethernet_5F00_Length-Match-report.zip & e2e.ti.com/.../Layout.zip image of the same for your reference. please let us know, if you have any concern on the same. - Vaibhav
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